XBAR0H

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Interpret as XBAR0H

SPI2NSSEN=DISABLED, XBAR0EN=DISABLED, UART0EN=DISABLED, UART1EN=DISABLED, SPI1NSSEN=DISABLED, SPI2EN=DISABLED, SPI1EN=DISABLED, AHBEN=DISABLED, UART0FCEN=DISABLED

Description

Crossbar 0 Control (High)

Fields

UART0EN	UART0 Enable. 0 (DISABLED): Disable UART0 RX and TX on Crossbar 0. 1 (ENABLED): Enable UART0 RX and TX on Crossbar 0.
UART0FCEN	UART0 Flow Control Enable. 0 (DISABLED): Disable UART0 flow control on Crossbar 0. 1 (ENABLED): Enable UART0 flow control on Crossbar 0.
UART1EN	UART1 Enable. 0 (DISABLED): Disable UART1 RX and TX on Crossbar 0. 1 (ENABLED): Enable UART1 RX and TX on Crossbar 0.
SPI1EN	SPI1 Enable. 0 (DISABLED): Disable SPI1 SCK, MISO, and MOSI on Crossbar 0. 1 (ENABLED): Enable SPI1 SCK, MISO, and MOSI on Crossbar 0.
SPI1NSSEN	SPI1 NSS Pin Enable. 0 (DISABLED): Disable SPI1 NSS on Crossbar 0. 1 (ENABLED): Enable SPI1 NSS on Crossbar 0.
SPI2EN	SPI2 Enable. 0 (DISABLED): Disable SPI2 SCK, MISO, and MOSI on Crossbar 0. 1 (ENABLED): Enable SPI2 SCK, MISO, and MOSI on Crossbar 0.
SPI2NSSEN	SPI2 NSS Pin Enable. 0 (DISABLED): Disable SPI2 NSS on Crossbar 0. 1 (ENABLED): Enable SPI2 NSS on Crossbar 0.
AHBEN	AHB Clock Output Enable. 0 (DISABLED): Disable the AHB Clock / 16 output on Crossbar 0. 1 (ENABLED): Enable the AHB Clock / 16 output on Crossbar 0.
XBAR0EN	Crossbar 0 Enable. 0 (DISABLED): Disable Crossbar 0. 1 (ENABLED): Enable Crossbar 0.

Links

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